Abstract
Discrete Fourier Transform (DFT) plays a very important role in the research area of signal processing, such as orthogonal frequency division multiplexing (OFDM) systems, spectrum analysis, multi-media systems and so on. Many topics on the implementation of DFT are discussed, which can generally be divided into two categories. One is the pipelined systolic array architecture, and the other is single signal processing element architecture based on memory. This article focuses on the implementation of DFT and IDFT which transform the signals between time and frequency in OFDM system. Because we care more about speed than the size of area, we use systolic array to implement DFT. Through this architecture, N-point DFT can be done in N clock cycles while the Butterfly architecture in NlogN clock cycles. The other topic on the thesis is the implementation of maximum likelihood sequence estimation equalizer (MLSE) with systolic array. From the point of view of detection and estimation theorem, minimum symbol error probability could be achieved if the ML receiver is employed. When the signals are independent, the ML receiver and the symbol-by-symbol detector both are the optimum receivers. However, when the signal has memory, the performance of the symbol-by-symbol detector is worse than the ML receiver. In order to reduce the computation complexity of MLSE, this article presents the implementation of MLSE combined with the trace-back Viterbi algorithm using systolic array.