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應用新式頻率補償架構之整合式CMOS低壓降穩壓器
Thesis

應用新式頻率補償架構之整合式CMOS低壓降穩壓器

吳相翰
Masters, National Tsing Hua University
2006

Abstract

低壓降穩壓器頻率補償整合式電源管理
AbstractAs the larger requirement for low power portable electronic devices, power management becomes a popular solution for extending the battery life. Low dropout regulator (LDO) is a fundamental block of power management due to better load transient response, small output voltage ripples, and small area. However, it still suffers form some problems such as low efficiency, stability, and hard to integrate. Therefore, this thesis will introduce the design challenge of LDO regulators and proposed two compensation schemes to solve these problems.First, we will introduce some terms, definitions, fundamental concepts and design considerations about the LDO regulator. Next, we propose a frequency compensation scheme for LDO regulator by a novel voltage control current source (VCCS). This LDO occupies lower quiescent current, have better transient response, and can extend the stable region of different ESR value of output capacitor.Next, a capacitor-free LDO regulator with transient response enhancement is proposed. This LDO regulator can operate whether an off-chip output capacitor is added or not and the stable region is extended. The detailed mathematic analysis is described clearly. In addition, a dynamic gm boosting block is presented to maintain the stability even with zero output loading condition. A slew rate enhancement circuit is proposed to reduce the voltage dips when a large output current loading increasing suddenly.

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