Abstract
With the development of mobile device towards low-power design and multi-function design. Also, transistor size is shrinking continuously based on Moore’s Law, the cost and difficulties of chip fabrication are getting higher and higher. Duo to these demands and problems, 3D Integration Chip (3D IC) by using TSV (Through Silicon Via) technology become the most popular research topic. However, the technology of 3D IC hasn’t fully developed yet. Lower yield and high cost are the bottleneck of mass production. Therefore, 2.5D Interposer Integrate System IC is proposed which has advantages like low cost and fabrication easily. Chips on 2.5D Interposer Integrate System communicate with each other by redistribution layer. But when chip once mounted on interposer, we can’t test whole system performance and whether the redistribution layer is open or short. We proposed a timing characteristic extraction methodology for 2.5D interposer integrate system. Using the transceiver and receiver circuit inside chip and data processing circuit to extract the timing characteristic of each block.