Abstract
Semiconductor manufacturing technology has evolved drastically in past decades, resulting in the popularization of personal and portable electronic devices. Almost all electronic devices need Non-Volatile Memory (NVM) to meet storage requirement since important information need to be kept when power is cut off. Meanwhile, single NVM memory chip is converted into embedded NVM (eNVM) chip gradually. Hence, the area of circuits can be reduced efficiently, making electronic products lighter, thinner and more competitive. Nevertheless, Flash memory, which composes mainstream of NVM products, has confronted lots of challenges in 90nm technology and beyond, including gate oxide leakage, high operation voltage, capacitive coupling and oversized area. Besides, comparing to pure logic process, traditional NVM devices require a dozen of masks and additional process steps, which will rising costs, and leads to yield and reliability concerns. However, this thesis has presented another novel One-Time Programmable (OTP) memory cell, fully compatible with CMOS logic process, thus it does not need any additional mask. This memory cell is fabricated by placing two series gates as close as possible. By doing so, Self-Aligned Nitride (SAN) is formed by the merged spacer of two series transistor, as charge storage node; therefore, it is named SAN memory cell. The SAN cell uses Source-Side Injection (SSI) as program mechanism, which is controlled by Program Gate (PG) and Select Gate (SG). Band-to-Band Hot Holes (BBHH) as erase mechanism are also discussed for the evaluation of Multi-Time Programmable (MTP) operation. SAN memory cell has exhibited its excellent features of low power, simple process and small area. Moreover, since Silicon Nitride is used as storage material instead of Poly Silicon, the gate oxide thickness can be reduced further. This makes SAN memory cell be promising candidate in scaled technologies.