Abstract
An improved sequencial controlled circuit is designed and implemented to measure the package stress effect on MOS transistors. It employs the characteristics of shift register and transmission gate to measure the characteristics of MOS devices. For resolving the issue of voltage drop due to routing, it utilizes the Kelvin measurement. The transistors under test include NMOSFETs and PMOSFETs, both with different channel widths and lengths, also included is LOD (Length of Diffusion). This circuit has only 13 probing pads and the total area for each measured circuit is 600um×500um. The measured circuits are placed in different locations within the chip for observing the stress effect in different locations. The purpose of the experiment is to research the MOS transistors’ characteristics change before and after package process. The silicon process is the mainstream 65nm low power logic CMOS process and the package type adoped is Flip-Chip packaging.