Abstract
The rapid progress in semiconductor technology allows the integrated circuits operating with high speed, low power, and complex functions. However, scaling of device feature size is approaching the physical limitation, and the continuation of Moore’s Law becomes questionable. The concept of three-dimensional integrated circuit (3D IC) attracts significant interests recently from both industries and academia. By stacking chips three-dimensionally, the problem of long interconnects in conventional 2D circuits can be resolved, and circuits with high operation speed and small form factors can be expected using 3D IC technology. However, one major issue for high speed signal transmitting in 3D IC is the Through Silicon Via (TSV). Owing to the limitation of processing technology and pitch size, the impedance mismatch between TSV and 2D transmission line could cause inter-symbol interference (ISI), form a standing wave, and seriously degrade high speed signal transmission. Also, the parasitic capacitances existing between the sidewall oxide layer and the substrate become a conducting path at high frequencies, leading to significant signal loss. These problems could be more pronounced as the TSV pitch size keeps scaling. In this study, we propose of using active equalizer to compensate the signal loss through the TSV in 3DIC for high speed data transmission. The second issue for high speed signaling in 3D IC is how to further increase the data rate of transmission and also keep the signal integrity. A dual-channel transmission is an effective approach to increase the speed of transmission. Use different frequencies (RF and Baseband), two sets of signal can be transmitted within a physical channel simultaneously. As a result, not only the transmission speed can be increased, but the power consumption of each bit can be reduced significantly. In this study, the signal transmission at the RF frequency will be investigated and will be combined with the baseband transmission in the future. With the 3D IC technology, the through silicon via (TSV) can replace the bond wires to connect the transmitter to the receiver for high speed signaling between different chip layers. The prototype of the circuit is implemented first using the flip chip approach, because of the difficulty to access the 3DIC technology. Another focus of this thesis is the design and optimization of three-dimensional inductors and the transformers for high speed wireline transceivers in 3D IC technology using TSVs. For the overall system, the chip area is a critical design concern. In this project, we will use the 3D inductive components to minimize the chip area with low power consumption and low noise. In this paper, we propose two circuits and one high speed signal transmission in 3D IC technology. The first circuit is 3D passive fliter, the operating frequency is at 140GHz, loss is less then -3dB, and the S11 is less then -10 dB. Another circuit is a three-dimensional integrated circuit high-speed data transmission active equalizer. The peaking gain is at 2.5GHz. When the transmission rate at 5Gb/s, jitter is about 22.6ps. And the RF band high speed signal transmission in 3D IC technology, which transmission rate at 4Gb/s, jitter is about 68ps, area is about 0.3mm2.