Abstract
For low-density parity-check (LDPC) decoders using the min-sum algorithm, the first two minimum values and the first minimum index must be found when updating the check node. Conventionally, this minimum-value finder is implemented digitally using a tree-structure scheme. In this thesis, we propose time-domain minimum-value finders, which process the mixed analog and digital signals. In addition, we propose digital to time converter (DTC) that firstly computes the signal of the most significant bit (MSB) in order to reduce the area of the delay elements. Compared to the conventional tree-structure-based scheme, the proposed time-domain minimum-value finders can reduce chip area and latency by more than 30\%.