Abstract
Simulation provides a way to help developers to validate the performance and functionality before the hardware prototype is built. It is a useful tool to analyze, operate and design embedded systems. However, when more and more components are added into the simulation system, the simulation performance will greatly be reduced. In order to boost up the simulation speed, we propose a multicore simulation framework with component simulators running concurrently. The proposed multicore simulation framework includes an AndesCore, multiple PAC-DSPs, and other hardware devices. AndesCore and PAC-DSP are both ingenious IP design from Taiwan Star IP program. The proposed multicore simulation framework is based on the SID simulation framework, which is an open source simulation framework for system simulation. The original design of SID is a single thread simulator. Each processor component is executed with certain step cycles which is predefined in configuration file. Thus, the simulation performance degrades significantly as the number of simulated processor increases. To overcome this problem, we develop a PACManager component to map each PAC-DSP to host thread. PACManager component has to maintains the shared resources accessing for each PAC-DSP. The synchronization point only happens while PAC-DSP tries to access shared resources. Therefore we achieve the constant simulation performance as the number of simulated PAC-DSPs increases. Also, the power consumption is a big issue for embedded system. However, the well-known simulation tool such as SID and QEMU don’t support the power information. In comparison, our proposed multicore simulation framework provides the power profiling information in simulation system. We collect the execution trace and state of hardware components in the simulation environment. It helps the developers to use the power profiling information from simulation to optimize the design for power consumption. In the experiments, an matrix multiplication application and an application based on human face RMS (recognize, mining and synthesis) scheme are deployed as a running example. We run the simulation at a Intel(R) Core(TM) i7 8-core host machine. The experiment result shows our simulation performance will remain constant through varying the number of PAC-DSPs from 1 to 8. The proposed multicore simulator provides the full system simulation for developing multicore embedded application. Also, it is helpful for the developers to verify the design and observe the power consumption information for application.