Abstract
A 10-bit 50-MS/s pipelined analog-to-digital converter (ADC) using an operational amplifier sharing technique in TSMC 0.35µm standard CMOS process technology is presented. A new method to suppress the effect of kickback noise in the low offset comparator is also presented. The simulated ADC performances achieve -85 dB of Noise Level,-65.5 dB of THD、59.8dB of SNDR for 1.28 MHz input signal. Under 2.5-V supply, the power consumption of the proposed ADC is 31-mW. The measured ADC performances achieve -60 dB of Noise Level,-25.5 dB of THD、22 dB of SNDR for 2 MHz input signal. Under 3-V supply, the power consumption of the proposed ADC is 50-mW. The chip area including I/O pads is 3.45 mm2.