Abstract
In this paper, a new structure of the nonlinear PFD is proposed to achieve fast lock as well as small output jitter. The proposed Piecewise-Linear PFD has more flexibility than previous designs, since the lock time and the output jitter of the PLL are no longer tradeoffs. When the phase difference of the reference and the feedback signal is larger than π, additional charging or discharging current is injected to the loop filter to accelerate the lock process. On the other hand, to keep the jitter small, the Piecewise-Linear PFD acts just like the conventional linear PFD while approaching lock. The concept of the nonlinear PFD has been discussed for a period of time to accelerate the acquisition time. Nevertheless, the structure of the nonlinear PFD is often more complicated than the conventional one. On the contrary, the existing simpler structures have their own disadvantages. The Piecewise-Linear PFD does not increase the chip area since the overhead is limited. The structure is simple but it does solve some flaws of the previous nonlinear PFD designs. In addition, the current source and current sink of two charge pumps in the proposed scheme have been proven to be the reasonable values by mathematical analysis. Thus, not only the stability but also the power consumption can be optimized. The post-simulation results show that a speedup of 68% can be achieved with comparison to the conventional PLL. Moreover, the jitter is almost the same. The output frequency of the PLL is up to 2.5GHz.