Abstract
This thesis is to implement hardware design of LDPC coded modulation with iterative demodulator and decoding system. Demodulator and decoder exchange information in iterative demodulator and decoding system to increase performance of LDPC coded modulation system. For hardware of demodulator, we proposed three approxmate methods to reduce hardware complexity of demodulator without significantly performance loss. Moreover, we lower the number of symbols simultaneously processed in demodulator to avoid unnecessary area increase. We adopt new layered decoding architecture compatible to our system to finish our LDPC decoder. To improve system throughput, two frames are in iterative demodulator and decoding system, and use hardware resource of demodulator and decoder by turns. Consequently, we achieve better throughput and throughput-area ratio(TAR) compared to non-iterative demodulator and decoding system.