Abstract
Abstract The topic of this thesis is to realize a wideband frequency synthesizer by standard CMOS 0.18μm process for WLAN applications. When we design the frequency synthesizer, we want to get the wider frequency tuning range, the better phase noise performance and the lower power consumption. Here, we want to realize a frequency synthesizer whose locking range is from 4.9GHz to 5.825GHz and the phase noise is -110dBc/Hz at 1MHz offset from the carrier. Besides, to avoid pulling and reduce LO-RF interaction for the real application in the RF transceiver, we use the two-thirds LO architecture here. Therefore, we must realize a frequency synthesizer whose locking range is from 3.267GHz to 3.883GHz and phase noise is -113.5dBc/Hz at 1MHz offset from the carrier first. We totally realize two chips in this thesis. The first chip is the voltage-controlled oscillator. The measured frequency tuning range is from 3.288GHz to 3.555GHz and from 4.608GHz to 5.066GHz. The measured phase noise is -115.9dBc/Hz at 1MHz offset from the carrier. The measured power consumption is 22.5mW. The second chip is the frequency synthesizer. After completing the design of the rest building blocks of the frequency synthesizer (including the phase frequency detector, charge pump, loop filter and frequency divider), we begin to estimate the stability and loop bandwidth by analyzing the system of the frequency synthesizer. Afterward, we analyze and estimate the total phase noise of the frequency synthesizer. The measured locking range of this frequency synthesizer is from 4.76GHz to 5.09GHz. The measured phase noise is -104.6dBc/Hz at 1MHz offset from the carrier. The measured power consumption is 22.9mW. Finally, the areas of the two chips are both about 1100×1100μm2.