Abstract
In this thesis, a fast-locking automatic gain control loop is implemented in 0.18μm mixed-mode CMOS technology for wireless communication applications. This loop adopts two concepts to enhance the fast-locking time. First, I/Q paths and the squaring function of Giordano,, are used to cancel AC ripple rapidly, instead of using low pass filter. Second, the feedback path of AGC loop is implemented with digital circuit for easily changing loop gain and reducing the capacitance area. The area of the experimental chip is 1.113 mm × 0.918 mm. The VGA in the AGC loop provide 60 dB gain range from -5.88 dB ~ 53.94 dB and has 24.1 MHz bandwidth at maximum gain setting. The total harmonic distortion (THD) and input referred IP3 at minimum gain setting are 32.14 dBc and 0.3 dBV. The tuning range of amplitude detector is from 1.437 V to 1.11 V when input signal amplitude is from 0 V to 0.4 V. The locking time of the AGC loop is less than 18.4 μs when the input signal operates in 1 MHz and the locking gain range is -4 dB ~ 40 dB and output swing is 0.8 Vppd.