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應用於生理訊號擷取系統之10-bit、1.28MS/s連續漸近式類比至數位轉換器
Thesis

應用於生理訊號擷取系統之10-bit、1.28MS/s連續漸近式類比至數位轉換器

林冠廷
Masters, 國立清華大學, 電機工程學系
2012

Abstract

類比至數位轉換器 連續漸近式類比至數位轉換器 電容式數位至類比轉換器 Analog-to-Digital Converter (ADC) Successive Approximation Register Analog-to-Digital Converter (SAR ADC) Capacitive Digital-to-Analog Converter (CDAC)
In recent years, the industry of the portable electronic devices for bio-medical signals monitoring has been significantly growing. For the requirement of these portable devices, low power dissipation and high hardware efficiency are the main goals of the circuit design for the bio-medical electronics. A 10-bit, 1.28MS/s successive approximation register analog-to-digital converter (SAR ADC) for the acquisition system of bio-medical signals is presented in this thesis. In this SAR ADC, the DAC is functioned by a tri-level monotonic switching capacitive architecture. Its average switching energy is 9.5% to that of conventional switching capacitive DAC (CDAC), while its capacitor amount is 25% to that of conventional switching CDAC. The SAR ADC was fabricated in TSMC 90nm CMOS technology. The whole chip area was 1mm2, while the core circuit area was 0.205mm2. At 0.7V and 1.28MS/s, the static experimental performance of this SAR ADC were DNL of 5.312/-1 LSB and INL of 6.559/-3.932 LSB; the dynamic experimental performance were SFDR of 56.51dB, SNDR of 47.13dB, and ENOB of 7.53 bit. The SAR ADC dissipated power of 9.44uW, and achieved FOM of 39.9fJ/conversion-step. For better performance, another 10-bit SAR ADC is presented and also fabricated in TSMC 90nm CMOS technology. To lessen the dynamic offset effect induced by asymmetric switching process of monotonic switching CDAC, the improved SAR ADC was formed by an offset adjustable comparator and a proposed tri-level alternative switching CDAC. The average switching energy of this CDAC was 13.5% to that of conventional switching CDAC. The whole chip area was 1mm2, while the core circuit area was 0.14025mm2. At experiment conditions of 0.5V and 1.28MS/s, this SAR ADC had DNL of 0.646/-0.929 LSB, INL of 1.556/-1.467 LSB, and its SFDR, SNDR, and ENOB were enhanced to 60.21dB, 50.78dB, and 8.14 bit, respectively. The power dissipation of this SAR ADC was 4uW, and the resulting FOM was improved to 11.078 fJ/conversion-step.

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