Abstract
Turbo Codes were recently proposed by Berrou, Glavieux, andThitimajshima as a remarkable step forward in low-complexity,high-gain coding. As a consequence, the 3rd Generation Partnership Project (3GPP) proposal employed turbo codes as the forward error-correcting code for services with high data rate above 32 kbps and BER range of 10^-3 to 10^-6.A turbo encoder is formed by parallel concatenation of two (ormore) recursive systematic convolutional encoders seperated by arandom interleaver. The turbo decoder applies iterative decoding scheme with different soft-output decoding algorithms.Our research is to focus on using digital signal processor (DSP) to implement the prime interleaver and turbo decoder structure. Thus, we first review the prime interleaver scheme, and then study the hardware and software features of the DSP system, including the data transfer in Daytona board by direct-memory-access (DMA) and efficient utilization of memory map of the processor so as to increase the turbo decoding speed. Besides, we also give some testing examples to prove that data located in internal memory have the fastest processing speed among that in other external ones.In our implementation process, we first show the simulation results of prime interleaver and its modified version with different block sizes. Moreover, we also present the profile statistics of turbo decoding speed to make some comparisons of the turbo decoder employing eight soft-output decoding algorithms which had been studied and improved previously with different block sizes. Also, to implement the turbo decoder structure on DSP, we also provide some key points for the implementation of the turbo decoder and describe how to make use of memory map of DSP processor in order to increase the decoding speed. Finally, we conclude this study and suggest some possible future researches.