Abstract
Turbo codes, which are considered as the most important research topic in the coding theory in recent yesrs, were proposed by Berrou, Glovieux, and Thitimajshima in 1993. It has a near-capacity bit error rate performance at low signal-to-noise ratios with acceptable computation complexity. A turbo decoder consists of two (or more) soft-output decodes connected by an interleaver and a deinterleaver. In this thesis, we propose a hardware structure for soft-output decoders with a unified algorithm and a two-backward-processor scheme. The unified algorithm offers a flexible structure suitable for different trellis-based soft-output algorithms. And thetwo-backward-processor architecture can be used to deal with theproblem of long time delay. Finally, we provide a hardware design and give an example of the decoder structure for the third generation mobile communication systems.