Abstract
In the System-on-Chip(SOC) designs, chips are composed of pre-designed cores for reducing time-to- market overhead. The complexity of test development is increased along with more cores inte-grated into a single chip. Moreover, cores used in SOC designs usually comes from diverse sources. Hence, to make core test plug-and-play comes true, a standardized interface between cores is very important. The IEEE P1500 working group works towards it. The test wrapper generator proposed in this thesis is based on top of IEEE P1500 Wrapper. Although IEEE P1500 has standardized wrapper, but it is still configurable. The test wrapper generator in this paper automate the wrapper generation, and has features of flexibility. A standard IEEE P1500 test wrapper has three basic components. Wrapper Instruction Register(WIR), Wrap-per Bypass Register(WBY), and Wrapper Boundary Register(WBR). The test wrapper generated can have different types of wrapper boundary register cells without modifying WIR. Besides, the scan chain count is easily adapted to the TAM width. The other focus point of IEEE P1500 is the Core Test Language (CTL), which is a standard language for the transformation of all test information needed to test a core from core provider to core user. The proposed test wrapper generator is able to transform the original bare core’s CTL file into a new one of wrapped core, too.