Abstract
It will take a long time to obtain error-floor results of Low-Density Parity Check Codes using software simulation. To shorten the simulation time, this paper uses FPGA-based emulation to evaluate the error-floor performance. Shuffled LDPC decoder is implemented using FPGA. The conventional shuffled decoder architecture is very large so that the FPGA resource is not enough. We reduce parallelism of the decoder to solve this problem. This paper proposes a new schedule method to achieve this goal. Approximate 27% of the total area is reduced. In addition, we propose a new preloading technique to increase throughput of the decoder. This new technique can provide an increased throughput so that the shorter simulation times can be achieved.