Abstract
The design of 6GHz CMOS fractional divider for frequency synthesis is discussed in this thesis.The architecture of the proposed programmable divider is based on connected divide-by-2/3 cells. The same cell structure is suitable for power optimization and also facilitates layout work. To realize the required logic function, MOS current mode logic is chosen for its high-speed operation characteristic and noise immunity. The necessary building blocks for frequency synthesizer application such as pre-amplifier and rail-to-rail circuit are also briefly described. Simulation results show that 6GHz operation frequency is achieved.On the other hand, to achieve fine channel resolution with no serious spurs due to fractional division, a sigma-delta modulator is proposed to randomize the division number. Through the behavior model built by Simulink software, the parameters of the modulator, such as noise transfer function and feed-forward coefficients are determined. Therefore, a single loop modulator with its NTF corner at 0.5 sampling frequency is chosen for better noise shaping.To verify the design circuit, an experimental chip is fabricated in UMC 0.18 m process. The measurement results are also illustrated in the thesis.