Abstract
ABSTRACT The demand of the high data capacity and high transmitting rate makes the operation frequency of the communication system increases rapidly. The frequency divider, typically used for phase-locked loop, plays an important role in a communication system. The frequency divider reduces the high frequency to low frequency for certain application. The main focus of this work is to design various frequency dividers based on a standard CMOS technology. The basic theory of the Phase Locked Loop (PLL) is introduced in the beginning, which illustrates the importance of a frequency divider, and the advantage of using high frequency divider for PLL. A fully integrated frequency divider is implemented by a 0.18-□m CMOS technology and demonstrates an operation frequency up to 20GHz for Local Multipoint Distribution System (LMDS) applications. The proposed frequency divider consists of both analog circuit and digital circuit with a function of divided by 4 in the frequency range from18.8GHz ~ 23.2GHz. Second, a frequency divider with active inductor is implemented in CMOS technology. The proposed frequency divider replaces the passive spiral inductor with active inductor to reduce the required chip area significantly. The methodology of source degeneration is used to increase the operation frequency. From measurement results, the proposed frequency divider has the function of divided by 2 in the frequency range from 5.4GHz ~ 6.4GHz. Compared with other works, this work has the smaller chip area under the same circuit topology. A frequency divider with feedback resistor is designed, which employs a feedback resistor to increase the operation frequency. From simulation results, the feedback resistor can increase operation frequency effectively. The proposed frequency divider can operate in the frequency range from 12GHz to 20GHz. Compared with other works, this work has the smaller chip area under the same operation frequency.