Abstract
The reliability of ultra-thin gate oxide has been researched for many years since the development of the VLSI technology into the sub-micron regime. Most of the studies following the conventional analysis of thicker gate oxide layer focus on the dielectric breakdown and the lifetime of a “single” device. Gradually, not only various degradation in device characteristics are observed but the physical mechanisms leading to these results are also well understood. However, the practical situation of the device when it is used in circuit configurations and the impacts of these degrading characteristics on circuits need to be studied or modeled. This thesis focuses on extending the reliability research from a device level onto a circuit level, i.e. the reliability of the device operating in circuits. This work will establish resistance models to simulate the degradation of the circuit performance resulting from devices’, and predict the reliability of the circuit, moreover, to provide different sets of the “Design Rule” for different applications.