Abstract
To scale CMOS field-effect transistors (FETs) well into the sub-20nm region, multi-gate structure, such as, FinFET is adapted as the mainstream technology solution for the suppression of short channel effects and maintaining high-gate control ability. However, due to the 3D structures, which are placed in close proximity, parasitic capacitance increases drastically. Unwanted and unavoidable parasitic capacitance exists in a transistor and limits device performance. Therefore, how to characterize and extract parasitic capacitance of FinFETs becomes an important issue. In this work, first of all, some capacitance measurement methods will be reviewed and point out all drawbacks of these measurement methods, and then a new parasitic capacitance measurement method by metal-gate coupling structure is proposed. By the relationship between sub-threshold swing and coupling ratio and a flash-memory-like test structure, FinFET parasitic capacitance can be extracted and calibrated.