Abstract
In this thesis, the electrical properties of Al/Pb(ZrTi)O3/insulator/Si capacitors and field effect transistors with various surface treatments were studied. The wafers were given a H2O2 pre-treatment before insulator layer deposition and a HCl post-treatment after deposition. For the case of Al/ZrO2/Si capacitors with surface treatments, the interface state density was reduced from 5.62x1013/cm2 to 4.0x1012/cm2 and the composite dielectric constant of ZrO2 film (about 7 nm) plus interfacial layer was increased from 5.54 to 7.3. The binding energy of the Zr-O bond was increased and the Zr out-diffusion was decreased based on X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) results, respectively.The leakage current density of Al/PZT/ZrO2/Si capacitors with both treatments was improved from 10-1 A/cm2 to 5.4x10-6 A/cm2 at 5 V and the retention time of Al/PZT/ZrO2/Si capacitors was improved from 13.3 hours to 17.1 days. The longer retention time of Al/PZT/ZrO2/Si capacitor with surface treatments was attributed to the reduced gate leakage current. The FeFETs with both treatments maintain a threshold voltage window of about 1.1 V after an elapsed time of 3000 sec. The subthreshold slope was improved from 311 mV/dec to 91 mV/dec. The drain current on/off ratio of FeFETs with both treatments was about 103. The improvements are most likely due to the reduction of the leakage current and the interface states at the ZrO2/Si interface.Al/PZT/Y2O3/Si FeFETs with both treatments were also fabricated. The leakage current density at 5 V is reduced from 10-3 A/cm2 to 10-6 A/cm2. Samples with no treatment show a much larger flat band voltage shift ΔVFB of 1.5 V compared to that of 0.8 V with both treatments. It means more electrons are injected into the insulator layer with no treatment as the positive bias is increased. The best FeFETs maintain a threshold voltage window of about 1.5 V after an elapsed time of 5000 sec. The drain current on/off ratio of FeFETs with both treatments after applying writing pulses of +8 V and -8 V with a duration of 100 ns was about 105. The improvements are most likely due to the reduction of the gate leakage current and the charge injection effect.