Abstract
The first half of this thesis describes the frequency synthesizer, and analyzed the differences between fractional frequency synthesizer and integer frequency synthesizer, and their advantages and disadvantages. About integer frequency synthesizer,if we decrease integer N, we will increase reference frequency, it will decrease frequency resolution but increase purity of spectral, so designer should make some choice about them, and then we describes how to use the Delta-Sigma Modulator effect to solve these shortcomings. In the Delta-Sigma Modulator side, respectively, this thesis also discuss first-order Delta-Sigma Modulator, high-order Delta-Sigma Modulator and multi-stage Delta-Sigma Modulator differences and then compare about the advantages and disadvantages when these three kinds of Delta-Sigma Modulators are placed into the fractional frequency synthesizer, as a design reference. The latter half of this thesis using digital circuit design flow and TSMC 65nm process to implement a MASH 1-1 multi-stage Delta-Sigma Modulator. After Verilog HDL code design, we complete Synthesis, APR, and the validation of Calibre, and then Tape Out. In addition, in order to enable it to get the application in high-frequency circuits, we also committed to enhance its clock speed, and finally its clock speed is be confirmed by Post-sim verification that reach more than 1G Hz.