Abstract
As technological process continue to evolve in recent years, from 180nm, 90nm, 65nm, 40nm until 28nm, while the dimension of device keeps on shrinking. However, process variations have a large impact on circuit performance by decreasing the rate of the product’s yield. While designing the early stage of circuit design, designers want to observe the effects of process variations using the Monte Carlo statistical analysis, which takes the device variations of circuit simulation into consideration. Nevertheless, it takes a lot of time to analyze the statistics of circuit in simulators such as HSPICE or SPECTRE, and even impossible for large circuits. In analog circuits, device matching of physical layout is very pivotal and we very concern the effects of process variation. Designers often use common-centroid to eliminate device mismatches. Nonetheless, these principles are only for reference during physical layout and do not follow an objective standard measurement. The parasitic effect of routing between devices is inevitable. The variation of device dimension, the matching arrangement of physical layout, and the parasitic effect of routing are factors that might cause the circuit’s yield to decrease. This thesis provides fast yield estimation software within the consideration of process variation. We can classify variations into three aspects: the variation of device dimension, the variation dependent on physical layout, and the parasitic effect. For each aspect, we use the Monte Carlo simulation to predict the effects of process variations. Moreover, our software achieves a faster version of Monte Carlo simulation. Therefore, we can have an efficient way of estimating the yield from three different aspects in the early stage of design, thereby providing designers with a choice when choosing the size of the device and layout arrangement. Hence, we can avoid redesigning the circuit or rearranging the physical layout. Other than to lower the cost of designing the product, we can improve the time to market.