Abstract
Extremely low error rate is required for storage systems. Trapping sets are regarded as the major cause of the error floor of low-density parity-check (LDPC) codes. In this work, a practical method is constructed for lowering the error floor of low-density parity-check (LDPC) codes. At first, an hardware simulator is implemented using FPGA (Field-Programmable Gate Array), and a large numbr of error samples can be collected along with the corresponding noise patterns. Based on the correlations between the noise patterns and code structures, the received bits can be cataloged and a table of {\it harmful blocks} is listed. When the error bits in the received sequence cannot be totally corrected using the formal decoding process, the LLR values of certain bits are adjusted, and a modified decoding process is excuted. The selections of the adjusting bits are based on the harmful block table. The total number of harmful blocks is equal to that of the block columns. The storage for harmful blocks can be significantly reduced. After sufficient error samples and noise patterns are collected, it can be observed that only a small part of the harmful blocks is enough to achieve a satisfactory error floor lowering capability, and the storage requirement is small. The proposed scheme has been evaluated with the assistance of the FPGA simulator, and the error rate can be reduced to less than 1\% of the formal decoding process.