Abstract
Almost all the transceivers adopt the 1:8 or 1:10 demultiplexing schemes due to the use of 8/10B CODEC. When integrating the transceiver with other high speed router or switch modules in a single chip, the 1:10 demultiplexing requires 320 MHz clock frequency to maintain the high data throughput rate. Therefore, we proposed a 1:20 transceiver IP that can reduce the operating frequency required in routers or switches by half. Most of the multiplexers are implemented with BiCMOS, silicon bipolar, GaAs, SiGe, etc. Though these technologies have advantages of speed over CMOS, many researchers try to make optical communication component using CMOS, due to its inherent advantages of price, power and compatibility. And they often adopt the tree-type structure for it is relatively easier to get faster speed than other structure and that is the most direct way to fulfill the function of SONET. But it can only serialize the parallel data with the bit number of 2’s power. In this thesis, we use the double edge triggered shift register structure. Through this structure, an any even number of N to 1 multiplexer can be realized easily. And we adopt the SCL circuits to raise the operation speed of the multiplexer. However, our multiplexer has both the features of high speed and high flexibility. This work has been implemented in a 0.18μm CMOS technology. The presented multiplexer design can achieve 6 Gbps data rate with 20:1 multiplexing and 20 picoseconds peak to peak jitter.