Abstract
The ever-increasing processing speed of microprocessor motherboards, optical transmission links, intelligent hubs and routers etc., is pushing the off-chip data rate into the gigabits-per-second range. CML I/O interfaces are becoming more and more popular with applications involving transceiver reaching data rates up to 2.5Gb/s or greater. The serial interconnect signals show a lot of high frequency attenuation, skin loss after propagation through long PCB trace on the backplane. At the transmitter, pre-equalizers alter the waveform due to low-pass response of the interconnect. Limiting Amplifiers (LA) are responsible to amplify the input signal to a sufficient voltage for the reliable operation of Clock Data Recovery (CDR).We deploy the current mode logic to implement a low power, area-efficient 10 Gb/s wide-band current-mode logic (CML) I/O interface for high-speed interconnect. This I/O interface consists of an input equalizer, a limiting amplifier, a CML output buffer and an output voltage-peaking circuit. Several wide-band techniques for this work are adopted to broaden the bandwidth and realize the circuit in 10Gb/s operation. The techniques include PMOS active load inductive-peaking, negative active feedback, Miller capacitances and Cherry-Hooper topology. These techniques can reduce 80% of the circuit area compared to the circuit area with on-chip inductors. The integration of the input equalizer and output voltage-peaking is also verified in this paper to provide robust I/O interface for high-speed interconnect and compensate transmission signal attenuation in the backplane. This work has been implemented in a 0.18um CMOS technology. The total power consumption of the I/O interface is only 70mW. The areas of the input and output interface are 0.02mm2 and 0.008mm2. The input interface can operate at 10Gb/s with 40dB input dynamic range and 4mV input sensitivity.