Abstract
Clock designs play an important role in modern VLSI designs. Among clock network designs, the buffered clock tree architecture is the most popular clock network design adopted in modern VLSI designs. In this thesis, we have proposed a new skew concept, connective skew. Since, the traditional clock skew definition is too pessimistic. Moreover, we have proposed two buffer sizing algorithm, genetic algorithm and gradient search algorithm with applying connective skew. The experimental results show that gradient search algorithm can be a good initial solution for genetic algorithm. Finally, we have incorporated our algorithms with the current cell-based design flow. Our optimization goal is to apply the connective skew to clock tree such that the power consumption of the circuit will be minimized under the same skew constraint. From experimental results, applying connective skew to clock tree buffer sizing program can achieve about 10% of power minimization than applying traditional clock skew. In summary, we can reduce the power consumption of real circuits’ clock tree by integrating our proposed clock tree buffer sizing approach into current cell-based design flow.