Abstract
As the demands for higher interconnections and shorter electrical path between chips have increased, the emerging technologies are required to break through the limitation of conventional package technology and performance. In recent years, three-dimensional (3D) integration has been widely studied. Chip or wafer stacking combined with through silicon via (TSV) technology become an effective and potential solution due to the vertical interconnections and multi-function. Although 3D-IC/Package structure provides high performance and heterogeneous characteristics, the major problems of heat dissipations and its corresponding thermal induced stresses still remain. In this Research, we refer to the design concept and structure of 3D IC/Packaging of Industrial Technology Research Institute (ITRI) and Association of Super-Advance Electronic Technologies (ASET) to create the baseline finite element model. In order to assess the thermal-mechanical characteristic of 3D chip stacking structure, the finite element analysis (FEA) with parametric study in process modeling, package level, and board level is carried out. Futhermore, the factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information and interaction relationship between factors of the structure. In order to validate the fininte element analysis, Twyman-Green Interferometer is used for mearsuring the pre-warpage of chips. Compare the simulations and experiments, the results indicate the finite element method can be used to describe the mechanical behaviors of real structure. From the structure analysis in this research, the simulation results indicate that the diameter of Copper vias and thickness of chip are the major factors which influence the reliability of the 3D stacking structure the most. Based on the reliability assessment, the design windows of the chip stacking structure are established. Finally, the results of this study may provide a design guideline and a useful reference for future research.