Abstract
In semiconductor manufacturing, the manufacturing parameters are recorded automatically to provide information to engineers. But it is hard to find out the root cause of the problem from the enormous database. The engineers cannot response quickly when problems occur. To build up the knowledge database by analyzing and transforming data into useful information has become the vital issues of yield management and improvement in semiconductor factory. The bin-map can provide clues to identify the cause when low-yield situation happens. We can trace to specific root cause depending on the different pattern types of bin-map. Nowadays, the recognition of bin-map is performed manually. The individual fatigue and emotion will affect the results of pattern recognition. Therefore, this research intends to develop a two-phase bin-map pattern recognition system. The first phase is using the bin-map pattern to get the wafers with systematic failed patterns via Spatial Signature Analysis. At the same time, the features extracted form systematic failed patterns serve as the inputs for constructing the neural network in the second phase. This research selects the better model from two trained models i.e., LVQ model, of neural network to recognize the center type, edge type, local type, ring type and line type.The developed methodology is verified with industrial data from a famous semiconductor company. The existing neural-network approaches for recognizing the bin-map patterns on the wafer are limited by the size and the orientation of bin-map patterns. The experimental results demonstrate that the proposed methodology can not only solve this problem by extracting features, but also effectively identify the bin-map patterns on the wafer.