Abstract
Recently, due to the rapidly developing of commercial electronics, the demands of fast and mass storage devices increase. The mainstream NVM that dominate the market nowadays, Flash, have suffered from a spectrum of challenges--current leakage, ultra-high apply voltage, and, most important, scale possibility. These barrier, paradoxically, serve as catalyst for full-bloom investigation on new memory technology, especially resistive random access memory, RRAM.As the CMOS process is reaching a limit with the planar structure, FinFET is needed to maintain the scalability and performance of logic integrated circuits.In this dissertation, we propose a embedded RRAM structure that is fabricated by advanced 16nm FinFET CMOS logic process. This memory cell is fully compatible with CMOS logic process without any extra process flow or mask. The new FIND RRAM exhibits a very low set voltage and reset current resulting from the field enhancement on fin corners. The set/reset disturb test, continuous read test, endurance and no reliability concern which guarantee this memory cell as the candidate for next generation. The random telegraph noise (RTN) generated by electron trapping/de-trapping on the stacking layers was also investigated to determine the RRAM switching mechanism. The RTN model makes it possible for parameter extraction from the measured data. Analyzing the extracted parameters and the measured results lead to a proposed trap-induced resistive switching model.