Abstract
During the years of integrated circuits (IC) development, floating gate device has been used to implement nonvolatile memories, such as EPROM, flash memory, etc. Due to its very good compatibility with standard CMOS process, since the 90's, floating gate device has been treated in some studies as an analog circuit element in the analog circuit design. As the technology moves into submicron and even deep-submicron processes, more attention needs to be paid to utilize floating gate device as an analog element. This study proposes a floating gate device that can be used in analog circuit design. This floating gate device has been fabricated in a single poly 0.18μm CMOS process, The proposed floating gate device is constructed with three P-channel MOSFETs. The device is programmed by ion impact hot electron, and erased by FN tunneling. In addition, erasing operation by channel hot hole injection mechanism is also studied. Experimental data of electrical characteristics during programming and erasing, device endurance, and data retention is given in this study. In order to simulate the characteristics of the floating device by SPICE in circuit design, this study build up a SPICE compatible effective circuit model of the floating gate device, by building up the hot electron injection current model and the FN tunneling current model. Experimental data is compared with simulation results to verify the accuracy of this effective circuit model. This model provides a simulation tool for using the floating gate device as an circuit element in the circuit design. This study concludes with a novel application of the floating gate device in analog circuit. To deal with many restrictions of traditional translinear circuits in standard CMOS process, this study proposes to utilize floating device as a solution. By modifying the current-voltage relationship of the transistor, reduction of errors from the translinear circuit are expected. Formula deduction and circuit simulation are both used to verify the feasibility.