Abstract
Semiconductor wafer fabrication facilities face a variety of challenges. The combination of shrinking device geometries and increasing interconnect levels is rapidly increasing process complexity. It is leading to higher manufacturing costs and longer cycle times. Cycle time is one of the most important issues in semiconductor industry. In wafer fabrication processes, batch process steps account for approximately 25%~ 30% of the overall cycle time. This is caused by the long process times, batch sizes, hot lots and the batching rule of the batch process. These batch processes machines such as furnace and wet bench has major impact on the total cycle time. Comparing to batch process machines, single wafer process (SWP) machines enable shorter cycle time to promote faster product development, quicker ramp up of new products and earlier yield correction leading to economic benefits. However, the cost/benefit tradeoff is the major concern for a Fab to replace batch process machines with single wafer process machines. This study uses discrete-event simulation and Taguchi methods to investigate optimal process factors (i.e. hot lot ratio, batching rule, time constraint, and etc) of batch process in furnace and wet bench areas. Results of simulation proved the batch process in furnace area and hot lot ratio have major impact on cycle time.This study attempts to find an optimal combination of batch process and single wafer process machines in furnace area. And given the same cost, an optimal combination of batch process and SWP machines can be found to reduce normal lot cycle time by 4.0~4.5% and hot lot cycle time by 6.1%~16.4%, and increase batch process capacity efficiency by 15.3%~~23.4%. The result of the study provides managers insights for the cost-effect of single wafer process machines. And the methodologies proposed can be used by practitioners to support the decision making for adopting single-wafer process machines.