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接觸點電阻式隨機選取記憶體單元與陣列之研究
Thesis

接觸點電阻式隨機選取記憶體單元與陣列之研究

徐立明
Masters, 國立清華大學, 電子工程研究所
2014

Abstract

電阻式記憶體 陣列 接觸點
Sells of tablets and smart phones are rising up significantly recently. HDD(Hard Disk Drive) in Personal computer components sell markets are also replaced gradually by SSD(Solid State Disk). Different types of memory are embedded in these devices, including Non-volatile memory, like flash, and Volatile memory, like Dynamic random-access memory(DRAM), and Static random-access memory(SRAM). In the category of Non-volatile memory, flash memory is facing plenty of problems nowadays, including high operating voltage, and long program/erase time. Besides, most of the memory requires specific semiconductor manufacturing process to be fabricated. Only memory like SRAM is fully compatible to CMOS manufacturing process technology. Therefore, finding a non-volatile, low operating voltage, and is compatible to CMOS manufacturing process has been a popular research topic. Based on 90nm CMOS logic process, we realized Contact Resistive Random Access Memory(CRRAM). Ultra small size, fully CMOS compatible, and great scalability are its main characteristics. By DC Sweep and AC pulse operation, we find the optimal operation condition. Over 100k cycling test and 1000 hours 150oC baking test guarantee CRRAM unit cell has no reliability concern. It fully shows that CRRAM has the potential to be the candidate of novel, non-volatile memory in the next generation. By changing the process slightly, the yield of CRRAM is expected to be improved. Incremental Step Pulse Programming(ISPP) is studied and implemented in the cycling test of the CRRAM in order to achieve the specific resistance level. By changing the threshold current, gradually changing resistance is achievable. Multi-level cell(MLC), can increase memory capacity. Finally, based on 90nm CMOS logic process, a 16Mbits CRRAM array is constructed and studied.

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