Abstract
Flow control mechanism controls buffer usage for packet transmitting from node to node. Speculative flow control has been proposed in [2]. First, we design and implement this flow control mechanism by Verilog HDL. We build up a buffered crosspoint network with speculative flow control in RTL for functional correctness and then implement the crosspoint network model into FPGA for real hardware simulation.We also discuss the influence of speculative flow control on performance. We build up a 4x4 mesh network models with credit-based flow control and speculative flow control by Verilog HDL in RTL level. We tune some parameters of the network model, such as buffer size, delay time between adjacent nodes and speculated packet size for evaluation. We also build up two types of traffic model for the mesh network to show the influence of traffic on the network. Hardware cost in FPGA and ASIC is also presented.