Abstract
In this thesis, an 8-bit folding and interpolating analog-to-digital converter (ADC) that converts at 10 MHz is simulated and implemented in 0.35- m CMOS technology. The digital error correction and the decoder techniques by multiplexer are presented in this thesis. The principle of decoder and error correction technique are also discussed and analyzed in detail. The interpolating technique of preamplifiers reduces the power consumption and area. Also, the digital error correction technique increases the SNDR. As the differential-nonlinearity (DNL) and integral-nonlinearity (INL) are less than 0.5LSB and1LSB respectively, the SNDR is 56 dB for input frequencies up to 4.87MHz at 10Msample/s.The folding and interpolating analog-to-digital converter achieves 7.05 efficient bits for 4.87MHz input at 10 M sample/s and the total power consumption is 235mW with 3.3V supply voltage.