Abstract
In such an era that IC technology develops rapidly, generating clock signals in a system is a very important topic. One of the common methods is the Phase Locked Loop (PLL). PLL can generate an very accurate clock signal. Following is the operating principle of the PLL: The VCO in the PLL will generate a clock signal and this signal will be sent back to the PFD. The PFD will compare the phase between the VCO output signal and the reference signal. If the VCO signal leads, the control voltage of the VCO will be lower. In the opposite, the control voltage of the VCO will be higher if the VCO lags. After repeating the above process, the control signal will finally locked and the VCO will generate a clock signal of a certain frequency. In this thesis I implement a PLL used in a radar array system. The function of this PLL is to provide the LO for a mixer. The working frequency is between 9-11GHz. The PLL is digital-type PLL. The PLL consists of Phase Frequency Detector, Charge Pump, Voltage Control Oscillator, Divider Chain and Delta-Sigma Modulator. There are three parts in this thesis: The first part introduces the function and building blocks of PLL. The second part introduces the implementation of the PLL. The final part is the simulation result and layout of the PLL.