Abstract
The endless demand of 3C products with better and better performance has pushed great advances in electronics technologies. What we have perceived is the continuous scaling down in sizes of devices with similar or even better performance. This means not only the shrinkage in lateral sizes but also devices with multi-layer or 3D-stacking structures. Scientists and engineers thus face severer interfacial issues which are more detrimental to device performance arisen from necessary annealing processing during fabrication. In this dissertation we aimed at exploring two interface problems, one is the diffusion-barrier against Cu metallization, the other the contact issues between electrodes and oxide in resistive random access memory (RRAM).Firstly, TaSiCx thin film was designed as the diffusion-barrier against Cu metallization because Cu, being the most common interconnecting metal in integrated circuits, is a fast diffusing element at high temperatures, especially for Si-based materials. The refractory carbon instead of nitrogen was added through a simplified co-sputtering without any reactive process thus easier composition control against the most commonly used nitride barriers. We succeeded in explored stacked film Si(100)/TaSi2Cx(23 nm, 22 at% C)/Cu with the failure temperature 850 oC for at least 5 minutes, and Si(100)/TaSi2Cx(5 nm, 16 at% C)/Cu with the failure temperature 750 oC for at least 1 minute. Bonding characteristics of the barrier compositions and interfacial reactions were explored.Secondly, Ti-added amorphous SiOx was studied as RRAM oxide incorporating different electrode materials (Pt, Cu, Ti, Al and TiN). The formation of Al2O3 at the interface Al/TiSiOx, evidenced by ESCA analysis, blocks the resistive switching behavior between Al top electrode and Pt bottom electrode. However, the resistive switching succeeds in stack Cu/Al(2 nm)/TiSiOx/Pt due to the diffusion of Cu into Al2O3 during Cu deposition. We proposed that Cu thus activates the Al2O3 as conducting media in the resistive switching to achieve successful resistive switching.Resistive material TiO2 was also investigated as RRAM oxide. Interfaces were created in various stacking structures: Pt/TiO2/Pt, Pt/Ti/TiO2/Pt, Pt/ TiO2/Ti/Pt, Pt/Ti/TiO2/Ti/Pt, Pt/TiO2/W and at various TiO2 thickness (15 nm, 25 nm and 50 nm). The inserted Ti was 5 nm thick to serve as an asymmetric interface and also expected to create the transient region rich in oxygen vacancy, to form Ohmic contact, instead of Schottky contact, at the Pt/TiO2 interface, thus to improve the resistive switching. From the results of Pt/Ti/TiO2/Pt and Pt/TiO2/W stacks, the position of Schottky contact significantly dominates the operation polarity of resistive switching, namely clockwise direction for Pt/TiO2/W stack and anti-clockwise direction for Pt/Ti/TiO2/Pt stack). We demonstrate the importance of interfacial properties in the switching performance of the RRAM.