Abstract
The thesis presents a unified hybrid architecture to compute the 8-point IDCT (Inverse Discrete Cosine Transform) of multiple modern video codecs—MPEG4, H.264/AVC, VC-1, and HEVC (under development). The proposed hardware sharing architecture requires lower hardware cost than that of the individual implementations and ensures the maximum circuit reuse during the computation. The proposed architecture design needs only adders and shifters to reduce the hardware cost significantly. The proposed method can increase the circuit sharing capability and further reduce the number of adders. Hence, the proposed 1-D transform core only needs 33(29+4) adders and 41(38+3) shifters. For verification, a TSMC 0.18-μm process is applied to implement this chip, and the maximum operating frequency of the proposed design is 133.3 MHz with the hardware cost of 19K gates.