Abstract
在本論文中，我們提出兩個可計算 N 點 ( N=2**n) 離散哈特利轉換 (discrete Hartley transform ) 之心脈式架構，其中一個是實現以二為基底的頻域打散式 ( decimation-in-frequency ) 快速哈特利轉換演算法，而另一個則是實現以二為基底的時域打散式 ( decimation-in-time )快速哈特利轉換演算法。我們所提出之每一架構只需用到log//2 N 個乘法器，但卻具有每 N 個時脈產生 N 個離散哈特利轉換之高輸出性能， 亦即每個時脈可產生一個轉換結果； 這些架構都擁有規則化與模組化的特性，因此非常適合以超大型積體電路來實現；另外，與現有相關的心脈式 /規則化架構做比較，它們在面積時間複雜度上有明顯的改善。 接著我們利用所提出的心脈式離散哈特利轉換架構， 設計出一個可實現頻域適應性濾波器的超大型積體電路架構。這個適應性濾波器架構包含 3 log//2 N +14個實數乘法器、 9 log//2 N +15 個實數加法器以及 10 個大小為 2N 字元組的隨機存取記憶體，而且每個時脈可產生一個濾波輸出，其中 N 是相對應的時域適應性有限脈衝響應濾波器之長度； 此一濾波器架構不但可以很容易以單晶片方式來實現，而且在即時處理應用上也頗具吸引力。 為了驗證所提出架構之可行性，我們還利用一0.6 微米 CMOS 標準元件庫，完成 64 點 離 散哈特利轉換架構之雛型晶片設計，此晶片之面積為 7.126 x 7.318 mm**2 ，而它的工作時脈最高可達 50 MHz 。In this thesis, we present two novel systolic architecturesfor computing the N-point discrete Hartley transform (DHT),where N is a power of two. One is based on theradix-2 decimation-in-frequency (DIF) fast Hartleytransform (FHT) algorithm, and the other isbased on the radix-2 decimation-in-time (DIT) FHTalgorithm. Each of these two architectures requireslog//2 N multipliers and can evaluate the DHT at a rate ofone complete N-point transform per N clock cycles (i.e.,one transform sample per clock cycle). Both of them possess thefeatures of regularity and modularity, and are thus wellsuited to VLSI implementation. As compared to existingrelated systolic/regular designs, the proposed twogain significant improvements in area-time complexity.With the proposed systolic DHT architectures, we alsopropose a VLSI architecture for realizing a frequency-domain adaptive filter. The proposed adaptive filteringarchitecture involves 3 log//2 N +14 real multipliers, 9log//2 N+ 15 real adders, and 10 RAM's of 2N words each toprovide a throughput of one filter output sample per clockcycle, where N is the filter length of thecorresponding time-domain adaptive FIR filter. It can easilybe realized in a single chip at the current state ofVLSI technology, and is attractive for use in real-timeapplications. With a 0.6 mm CMOS standard cell library, aprototype chip is designed for the proposed DIF-DHTarchitecture for N=64. The chip requires a die size of about7.126 x 7.318 mm**2, and its maximum allowable clock rate is upto 50 MHz.