Abstract
A novel p-channel gateless one-time programming cell is proposed. Its advantages include full compatibility with advanced CMOS logic technology, fast programming and read operations, and low power dissipation. This UV-erasable, p-type gateless storage node is based on a parasitic ONO structure comprised by Resistor-Protection-Oxide (RPO), Contact Etching Stop Layer (CESL), and Inter level Dielectric (ILD). The proposed cell contains a gateless storage node and a select transistor, and can be easily arranged into a NOR-type array. The operation mechanisms of the new proposed cell are channel hot hole induced hot electron injection (CHHIHE) for programming and ultraviolet (UV) exposure for erasing. 2D process and device simulation is also employed in this essay to provide insight to operation mechanisms of this cell, and reveal the first-hand device characteristics, determine the operation condition. The novel p-channel embedded gateless cell are demonstrate in 90nm CMOS technology in this study. The measurement results shows advantageous performance in fabrication cost and scalability than the transitional One-time Programmable memory, and suggest that this novel device is widely suitable for embedded nonvolatile memory application in advanced logic technologies.