Abstract
During the progression of integrated system on chip, the embedded nonvolatile memory (NVM), which does not need extra masks and to be fabricated by standard complementary metal oxide semiconductor (CMOS) process have been widely studied. Though there are many technologies and designs have been studied and developed for logic NVM applications, but until now, there is not an overall solution which can serve high program and erase performance, thin gate oxide of CMOS logic process constraint, and superior high endurance property with an acceptable cell size. This study proposes a brand-new cell structure and operation method to achieve the above merits with fully CMOS logic compatible technology and processes. The new logic-compatible differential self-selective program multiple-time programmable nonvolatile memory, which is using CHE program and CHH erase by controlling the voltage of SG and BL, the program/erase speed can be achieved within 2msec, and the cell also consists of 3 transistors only. Moreover, the on/off window is successfully risen up to 106 orders post 105 cycling stresses. In terms of reliability characterization, the cell has been verified to pass the criteria after 1000 hours of retention bake at 85℃, 120℃, and 150℃. Finally, the proposed new self-selective program method is able to increase the sensing window twice, to improve the reliability effectively, and to avoid the mismatch problem, further to simplify the circuit design by overhead reduction. The high performance differential-nonvolatile memory cell has been demonstrated and providing a very promising solution in logic NVM application beyond 0.18um nodes.