Abstract
Conventional flash memory has been themainstream VLSI memory for the past decade.However, as the gate length of flash devices scales into nano-scale regime, it is great challenge to continue the original scaling pace of conventional ‘Floating Gate’ flash memory due to the physical limit of the tunneling oxide and its related reliability issues. To overcome the bottleneck of scalability, the Charge Trapping Flash (CTF) memory offers a promising alternative to further scale flash memory technology. In this study, a new non-volatile memory cell with dual channels and charge traps is implemented and in CMOS process on 6-inch wafers. The cells were fabricated in the National Nano Device Laboratory(NDL).In this theisi, the memory cell’s operating mechanisms, operating conditions, and threshold voltage shift after program/erase are discussed. Finally, we discuss the feasibility of this new device.