Abstract
Abstract Recently there are a lot of studies and researches in bipolar junction transistor (BJT) technology with fully CMOS logic compatible process. CMOS technology is known applied for low standby power dissipation, high packing density, and easy processes. However, bipolar junction transistor (BJT) technology is able to provide higher switching speed, current drivability, and low-noise performance, in spite of consuming more power. To combine the two technologies is the superior solution for the IC design, i.e. the designers can therefore obtain the lower power dissipation and noise level but increase the circuit speed and performance in some cases. Currently, most BiCMOS (BJT plus CMOS) technologies must utilize high performance but complicate Vertical BJTs in CMOS process platform. This kind of combination will produce a lot of extra masking steps and very complicate process flow, the benefit of CMOS and BJT will be significantly declined owing to high cost and low yield concerns. A new high frequency logic compatible Vertical Bipolar Junction Transistor without any extra masks has been proposed in this paper. The new structure has low cost and CMOS logic compatible properties, and still remains the advantages of BJT in high switching speed, low noise, and high gain. The device and its high frequency measurement patterns have been fabricated and demonstrated by TSMC 0.18um logic process and fully characterized by this study. The new logic compatible vertical bipolar junction transistors include two kinds of the layout structures: RPO Align (RPOA) and Gate Self-Align (GSA) structure. The gate self-align structure consists of two parallel poly-Si gates for separating emitter and base regions, the following self-aligned implantation can easily form the emitter, base, and collectors without additional masks or process steps. A RPO align structure is similar to the previous Gate self-align structure but use RPO layer instead of poly gate formation. The structure is not suitable for self-aligned implantation for emitter and base formation but use the anti-LDD and anti-pocket implantations to define the emitter and base regions. The RPO Align BJT (RA-BJT) can achieve a current gain over 60 and 17.5/15.5 GHz for the fT/fmax. Moreover, the Gate Self-Aligned BJT (GSA-BJT) also can achieve a high current gain over 70 and 45 GHz for the fT/fmax according to the simulation of TSMC’s 90nm CMOS logic process. More comprehensive characteristics will be exhibited and in the papers.