Abstract
As technology improve rapidly, the operation rate and resolution of Nyquist Analog to Digital Converter (ADC) are getting faster and higher. Such as Flash ADC、Two-stage ADC、Pipelined ADC and Successive Approximation Register ADC. There is only one goal, to make the operation rate and resolution matched perfectly. We propose two kinds of ADC’s architecture in this paper. At first we propose a time analysis SAR ADC, which contain linear voltage control delay line and time to digital converter to replace voltage type comparator, get 7-bit resolution. The linear voltage control delay line take input signal difference as it’s input and generate delay time according to the amount of input signal difference linearly. After we get the delay time, time to digital converter can resolve it to digital thermal code. Thermal code go through an encoder change into binary code and send to control logic to make capacitor array subtract corresponding input signal difference, make input signal approach to each other rapidly. Which greatly reduce the operation time and the times of charge redistribution, save many power consumption. In order to improve the effect of capacitor mismatch, we add some redundant in the last 5-bit to calibration errors which cause by capacitor mismatch. At last we propose a high speed current mode pipelined ADC, it’s unlike traditional architecture which often use switch capacitor to provide signal gain. We use current mirror to replace operational amplifier, which increase to operation speed and reduce gain error. In the future, this current ADC may combine with time interleaved technology accomplish a 4GS/s 10-bit ADC in tsmc 65nm process.