Abstract
The main purpose of this thesis is to fabricate a high voltage 4H-SiC lateral junction field effect transistor. In order to reduce the specific-on-resistance and enhance the breakdown voltage, we use a two-zone design in the drift region, and field plates at the gate and the drain. Furthermore, we also use the semi-insulating substrate to reduce the substrate-assisted-depletion effect. By using the reactive ion etch to fabricate the two-zone structure, we can avoid the difficult implantation process in SiC. The measurement results show that the breakdown voltage increases with the drift region length. A two-zone SiC JFET with gate width of 200µm and a lateral drift-region length of 100µm can achieve breakdown voltage is 4199V. The specific-on-resistance of this device is 454 mΩ-cm2 .