Abstract
Abstract In this thesis, we demonstrate a novel high voltage lateral 4H-SiC MOSFET on a semi-insulating substrate with a two-zone RESURF structure to reduce the electric field near the gate oxide. Different from the traditional implanted two zone RESURF structure, we fabricate the two-zone structure by dry etching. Field plates are also employed at the gate and the drain to enhance the blocking voltage. Semi-insulating substrates are used to avoid substrate assisted depletion effect. The length of the drift region, channel, and the etching location of the two zone are designed in this thesis. Experiment results show that step bunching due to the high temperature activation has a significant influence on the on-resistance. The breakdown voltage increases with the drift region and the best achieved blocking voltage is 4400 V, which is the highest value ever reported on SiC lateral MOSFET to the author’s knowledge. Ron is only 19.2Ω-cm2, limited by the poor channel mobility. Ron decreases with temperature in all devices, indicating a large number of interface traps existing.