Abstract
In this work,the C-V characteristics of Au-Ta2O5-Si capacitors are studied in this experiment. Various issues related to the applications Ta2O5 as the gate dielectrics for deep submicron MOS transistors are investigated. The Ta2O5 films are deposited with plasma-enhanced CVD. The Ta2O5 capacitor is subjected to constant voltage stress.The flat-band voltage shift (△VFB) is -0.69V with no stress in 14nm Ta2O5 film. For 14nm Ta2O5 capacitors, the △VFB after +3V 5 min is reduced to -0.21V, but △VFB after -3V 1 min is increased to -0.95V. This phenomenon is explained by the trapping of electrons and holes. In addition, an analysis by bandd iagram for the characteristics of C-V curves shift is studied to explain the phenomenon of electron trapping and hole trapping during constant voltage stress. Transient current curves are measured to prove this model. The mechanism of oxide traps is also discussed by discharging transient current curves. The interfave state density is calculated by conductance method. The interface state density is 1013 cm-2 before RTA annealing,and this value change to 1011cm-2 after RTA annealing. In this study, Ta2O5 in used to fabricate a MOSFET device. The effort is failed. One of the problem is wet etching is the adhesion between positive photoresist and Ta2O5 is bad as the etching soluttion is (HF:H2O=1:5) and (HF:NH$F=1:2).