Abstract
In order to ensure IC products can go to the market smoothly and on time, function faultless and reliability are very important. But as we know, the key point is if they can pass ESD testing or not. Although some advanced processes help prompting IC performance with processes scaling down, it pays the expense of reducing ESD performance also. How to invent novel devices or circuits to provide a whole chip ESD protection in deep sub-micron technology is the main point in this thesis. In this thesis, a new ESD protection methodology for high frequency CMOS RF LNAs is in realized. An on-chip inductor is employed to drain off the hazardous ESD charge while tuning out the harmful parasitic input capacitance. Besides that, we propose the islanded drain NMOS transistor for ESD protection. Without any additional process steps and mask numbers, the novel structure utilizes islands to change current path in NMOS drain diffusion region to increase drain ballast resistance in salicide process. So it can promote GGNMOS transistor turn on more uniformly. In addition to increasing ballast resistance, the island structure also increases the area of impact ionization current. In aspect of simulation and experiment, it proves the structure indeed improving ESD protection ability of devices. ESD performance of the novel structure indeed apparently be improved under such a lot of effects. Moreover, the islanded drain structure also can substantially reduce layout area to achieve ESD testing requirement.